Analog & Mixed-Signal Design — Interview Q&A
Common Questions and Answers
Q: What is the "virtual short" (or "virtual ground") assumption in ideal op-amp analysis, and why does it make the gain equations from Overview so simple?
A: An ideal op-amp is assumed to have infinite open-loop gain and infinite input impedance, which leads to two practical consequences used to derive gain equations: no current flows into either input terminal, and the voltage difference between the two input terminals is effectively zero (a "virtual short") whenever the op-amp is in a stable negative-feedback configuration. This is exactly why the inverting amplifier's gain equation, Vout = -(Rf/Rin) × Vin, doesn't depend on the op-amp's own internal gain at all — the virtual-short assumption forces the inverting input to sit at the same voltage as the (grounded) non-inverting input, and from there the gain falls out purely from Ohm's law across Rf and Rin. It's an approximation (a real op-amp has finite, not infinite, gain and input impedance), but it's accurate enough for the vast majority of practical circuit analysis, which is why it's the standard first-pass method taught before more detailed non-ideal analysis.
Q: Why does analog and mixed-signal IC design commonly stay on older, "mature" process nodes (like 65nm or 180nm) instead of using the leading-edge nodes (2nm, 18A) covered in Physical Design & Fabrication?
A: (needs verification — recheck against current source) Industry sources consistently describe this as a deliberate, ongoing choice rather than analog design lagging behind: leading-edge finFET/GAA transistor nodes optimize specifically for digital switching speed and transistor density, which are largely irrelevant to analog design priorities like predictable linear behavior, well-characterized device matching, and low process variation — and advanced nodes actually make analog transistor behavior less predictable and more sensitive to nearby-element interference, working against what analog design needs. Mature nodes (65nm, 180nm, and even older) are fully characterized, well-understood by design tools, and significantly cheaper to fabricate on, and for many analog applications (automotive high-voltage circuits, sensor interfaces) an older node is the technically correct choice, not a compromise. This is presented as current industry consensus based on live-searched sources as of this research, not training-data recall — the specific nodes considered "mature" versus "leading edge" shift over time as fabs retire older lines and bring newer ones online, so this framing should be re-confirmed if revisited well after this content's research date.
Q: What is ENOB (Effective Number of Bits), and how does it differ from an ADC's nominal (advertised) bit resolution?
A: An ADC's nominal resolution (e.g., "10-bit") describes its ideal, theoretical SNR via the SNR = 6.02N + 1.76 formula from Fundamentals — 61.96 dB for a 10-bit ADC. But real ADCs have additional noise sources beyond quantization error alone (thermal noise, non-linearity, jitter), so their actually MEASURED SNR is typically lower than the theoretical ideal. ENOB inverts the same formula to answer "given the SNR this ADC actually achieves in practice, how many bits of TRUE resolution does that correspond to": ENOB = (measured SNR − 1.76) / 6.02. For example, a nominally 10-bit ADC that actually measures 58 dB SNR (below its 61.96 dB theoretical ideal) has ENOB = (58 − 1.76) / 6.02 ≈ 9.34 effective bits — meaningfully less than its advertised 10-bit resolution, and exactly the kind of gap between a datasheet's nominal spec and real measured performance that a mixed-signal verification engineer is responsible for characterizing.
Q: Why is device matching such a central concern in analog layout, in a way that doesn't have a direct digital-design equivalent?
A: Many analog circuits (differential pairs, current mirrors) depend on two or more transistors behaving IDENTICALLY — same threshold voltage, same current characteristics — because the circuit's function relies on precisely cancelling out common effects between matched devices. Physical Design & Fabrication's standard-cell placement cares about wire delay and area, but digital logic's correctness doesn't depend on two specific gates having identical electrical characteristics — a slightly slower AND gate still produces the correct logical result, just marginally later. An analog differential pair with mismatched transistors, by contrast, can produce a functionally wrong output — a real, not just slower, error. This is why analog layout uses specific matching techniques (common-centroid layout, identical orientation, shared thermal environment) that have no real digital-layout equivalent, and why analog and mixed-signal layout is often described as a genuinely different design discipline from digital placement-and-route, not just a smaller-scale version of it.
Q: Why is mixed-signal design (analog and digital blocks on the same chip) considered harder than designing either domain in isolation?
A: The core problem is noise coupling: digital circuits (everything from HDL — Verilog & VHDL through Physical Design & Fabrication) switch rapidly between 0 and 1, injecting sharp current spikes into the shared silicon substrate and power/ground network every time a gate switches. Analog circuits are, by design, sensitive to small voltage variations — that digital switching noise can directly corrupt a sensitive analog signal sitting on the same die, an effect with no equivalent when either domain is designed in isolation. Real mixed-signal designs use dedicated techniques to manage this — separate analog and digital power/ground domains, guard rings, physical separation on the die, careful floorplanning (extending Physical Design & Fabrication's floorplanning concept specifically to keep noisy digital blocks physically distant from sensitive analog blocks) — none of which are needed in a purely digital or purely analog design.
Q: What is CMRR (Common-Mode Rejection Ratio), and why does it matter for a differential amplifier?
A: A differential amplifier is meant to amplify only the DIFFERENCE between its two inputs while ignoring any signal common to both (e.g., shared noise picked up equally by both input wires, or a shared DC offset). CMRR measures how well it actually achieves this in practice — the ratio between the amplifier's differential gain (how strongly it amplifies genuine input differences) and its common-mode gain (how much unwanted common-mode signal leaks through anyway), usually expressed in dB. A high CMRR means the amplifier is very good at rejecting shared noise and passing through only the genuine signal difference — critical in applications like sensor interfaces, where a real signal (e.g., a small voltage difference from a sensor) needs to be extracted from a noisy environment where both input lines pick up similar interference.