Physical Design & Fabrication — Intermediate

Overview's STA calculation assumed both flip-flops in every path see the clock edge at exactly the same instant. Real clock signals don't arrive everywhere on a chip simultaneously — the physical wires distributing the clock have their own delay, just like the data wires Fundamentals covered, and the difference in clock arrival time between two flip-flops is called clock skew. This page extends Overview's exact timing formula to account for it, and introduces Clock Tree Synthesis (CTS), the physical-design step that exists specifically to control it.

Analogy — Imagine a stadium announcer's voice reaching every seat instantly versus a real stadium where sound physically travels, arriving at the front row a fraction of a second before the back row. Clock skew is exactly this "sound travel time" difference, but for the clock signal reaching different flip-flops across a chip. If the delay difference happens to favor a particular signal path's timing, skew HELPS that path; if it works against it, skew HURTS it — the same skew number can be beneficial in one direction and harmful in the other, depending on which flip-flop's clock arrives later.

Clock Skew — Defined

CLOCK SKEW = the difference in clock arrival time between the
"launch" flip-flop (where a signal starts a path) and the "capture"
flip-flop (where it's received) for a given timing path.

If the CAPTURE flip-flop's clock arrives LATER than the LAUNCH
flip-flop's clock (positive skew, from the capture side's
perspective), the capture flip-flop effectively gets MORE time to
receive a stable signal -- skew HELPS this path's setup margin.

If the CAPTURE flip-flop's clock arrives EARLIER than the LAUNCH
flip-flop's clock (negative skew), the capture flip-flop has LESS
time -- skew HURTS this path's setup margin, and the minimum clock
period must grow to compensate.

Overview's original formula assumed zero skew (both flip-flops see
the clock edge simultaneously) -- a simplification. The real,
skew-aware setup formula is:

  min clock period = clock-to-Q + combinational delay + setup + skew

where skew is added when it hurts the path (negative from the
capture side) and subtracted when it helps (positive from the
capture side).

Annotated Example — Applying Skew to Overview's Critical Path

Overview's Path B (memory read → register) had a 11.7 ns minimum clock period with zero assumed skew. Suppose the clock tree actually delivers the clock 0.3 ns LATER to the capture flip-flop than the launch flip-flop (unfavorable skew for this specific path).

Given:  Overview's Path B base total = 11.7 ns
        unfavorable skew = +0.3 ns (added, since it hurts this path)

New minimum clock period = 11.7 + 0.3 = 12.0 ns
New maximum clock frequency = 1 / 12.0 ns = 83.3 MHz

Verified computationally: adding 0.3 ns of unfavorable skew drops
the chip's maximum frequency from Overview's 85.5 MHz down to
83.3 MHz -- skew alone, with no change to gate delay or wire RC
delay, measurably hurt the chip's real maximum operating frequency.

Clock Tree Synthesis (CTS) — Why It Exists

CTS is the physical-design step, run after placement (Overview),
whose entire job is DELIVERING the clock signal from a single source
to every flip-flop on the chip with MINIMAL skew -- typically using
a balanced tree structure (an "H-tree" is the classic textbook
shape) where every flip-flop is roughly the same wire-distance from
the clock source, so clock arrival times stay close together across
the whole chip.

This directly connects to Fundamentals' RC-delay material: clock
wires are real physical wires too, with their own resistance and
capacitance -- CTS specifically manages and balances THAT delay
across thousands to millions of flip-flops simultaneously, rather
than leaving clock arrival time to chance the way an unmanaged,
naturally-routed clock signal would.

Try It (2 Minutes)

Using the same Path B base total (11.7 ns), suppose CTS instead delivers a FAVORABLE skew of 0.3 ns for this specific path (the capture flip-flop's clock arrives 0.3 ns earlier relative to the launch flip-flop, in the direction that helps).

You should land on: new minimum clock period = 11.7 − 0.3 = 11.4 ns, new maximum frequency = 1/11.4ns ≈ 87.7 MHz — better than Overview's original 85.5 MHz. But a physical designer can't make every path favorable simultaneously because skew is a RELATIVE, path-specific quantity — the exact same clock-tree adjustment that delays a flip-flop's clock arrival (helping paths that CAPTURE at that flip-flop) simultaneously changes that same flip-flop's role as a LAUNCH point for other paths starting there, potentially hurting those instead. This is why CTS targets balanced (near-zero) skew everywhere as the safe default, rather than trying to hand-tune favorable skew onto specific known-critical paths, which real advanced flows do attempt (called "useful skew") but only very selectively, given this exact tradeoff.

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