Without pipelining, an instruction goes through 4 stages (Fetch,
Decode, Execute, Writeback) one at a time, and the NEXT instruction
can't start until the current one fully finishes all 4 stages.

  5 instructions x 4 cycles each = 20 cycles total (no overlap)

With pipelining, once instruction 1 moves from Fetch to Decode, a
NEW instruction can enter Fetch immediately — the 4 stages run on
different instructions simultaneously, like the car wash's 4
stations.

  Total cycles = (number of pipeline stages) + (number of
                  instructions - 1)
               = 4 + (5 - 1)
               = 8 cycles total

Verified: 20 cycles (non-pipelined) vs 8 cycles (pipelined) for the
same 5 instructions — a 20/8 = 2.5x speedup. Note this speedup grows
toward the stage count (4x, in this example) as MORE instructions
are added — the "+((n-1))" overhead of filling the pipeline the
first time matters less the longer the pipeline stays full.

Every flip-flop in an RTL design (the state register from Overview,
for example) has two timing requirements from Digital Logic
Fundamentals and HDL's sequential-logic material, now made concrete:

  CLOCK-TO-Q DELAY  — after a clock edge, how long until the flip-
                       flop's output actually changes (not
                       instant — real hardware has delay)
  SETUP TIME         — how long BEFORE the next clock edge the
                       flip-flop's input must already be stable, or
                       the flip-flop may capture garbage

Between two flip-flops sits combinational logic (the next-state and
output logic from the FSM example) with its own propagation delay —
the same idea as gate delay from Digital Logic Fundamentals, just
now summed across a real logic chain.

Minimum clock period = clock-to-Q delay + combinational path delay
                        + setup time

This must hold for the SLOWEST (longest-delay) combinational path
in the whole design — the "critical path" — not the average or the
fastest one. One slow path anywhere in the chip limits the clock
speed for the entire chip.

Combinational path delay = AND + OR + XOR
                          = 2 + 3 + 2
                          = 7 ns

Minimum clock period = clock-to-Q + combinational delay + setup
                      = 1 + 7 + 1
                      = 9 ns

Maximum clock frequency = 1 / (minimum clock period)
                         = 1 / 9 ns
                         = 0.1111 GHz
                         = 111.1 MHz

module counter_4bit (
    input  wire clk,
    input  wire rst,
    output reg [3:0] count
);
    always @(posedge clk or posedge rst)
        if (rst)
            count <= 4'b0000;
        else
            count <= count + 1;  // wraps automatically: 4-bit
                                  // arithmetic overflow at 1111+1
                                  // rolls back to 0000
endmodule

Trace over 18 clock edges, starting from count = 0:
  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1

Verified computationally: the counter reaches 15 (1111 binary) after
16 edges, and the 17th edge wraps back to 0 -- exactly the two's-
complement-style modular arithmetic from Digital Logic Fundamentals
(15 + 1 = 16, which doesn't fit in 4 bits, so the carry-out is
discarded and the result is 16 mod 16 = 0), just now happening
automatically on every clock edge instead of being computed once by
hand.