HDL — Verilog & VHDL gave you two isolated primitives:
  COMBINATIONAL LOGIC  →  assign / dataflow statements (the mux)
  ONE FLIP-FLOP         →  always @(posedge clk) Q <= D;  (memory
                            for exactly one bit)

RTL Design composes both primitives into something bigger, with a
name every real chip uses:
  STATE REGISTER   — a group of flip-flops (from HDL) holding which
                      state the FSM is currently in
  NEXT-STATE LOGIC  — combinational logic (from HDL, and ultimately
                      Digital Logic Fundamentals' Boolean algebra)
                      computing which state comes next
  OUTPUT LOGIC      — combinational logic computing the output,
                      either from state alone (Moore machine) or
                      from state AND current input together (Mealy
                      machine, used in the example below)

This is not a new circuit primitive — it's the same flip-flop and
combinational-logic vocabulary from the previous two technologies,
arranged into a specific, named, reusable pattern.

MOORE MACHINE                      MEALY MACHINE
Output depends ONLY on the         Output depends on the CURRENT
current state.                     STATE and the CURRENT INPUT
                                    together.
Output changes only when the       Output can change as soon as the
state changes (after a clock       input changes, even before the
edge).                              next clock edge.
Generally needs one MORE state     Generally needs FEWER states for
than the equivalent Mealy design   the same behavior, but the output
(to give the output its own        is more sensitive to input timing
dedicated state).                  glitches, since it reacts
                                    immediately to input changes.

Neither is universally "better" — it's a real design tradeoff
between state count and output-timing behavior, and both types
appear regularly in real designs.

module seq_detector_101 (
    input  wire clk,
    input  wire rst,
    input  wire bit_in,
    output reg  detected
);
    // Three states: S0 = no progress, S1 = saw '1', S2 = saw '10'
    parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;
    reg [1:0] state, next_state;

    // STATE REGISTER — exactly the flip-flop pattern from HDL,
    // now holding 2 bits instead of 1
    always @(posedge clk or posedge rst)
        if (rst) state <= S0;
        else     state <= next_state;

    // NEXT-STATE AND OUTPUT LOGIC — combinational, Mealy-style:
    // 'detected' depends on state AND bit_in together
    always @(*) begin
        next_state = state;  // default: stay put
        detected = 1'b0;     // default: no detection this cycle
        case (state)
            S0: next_state = bit_in ? S1 : S0;
            S1: next_state = bit_in ? S1 : S2;
            S2: if (bit_in) begin
                    next_state = S1;
                    detected   = 1'b1;  // completes "101" this cycle
                end else begin
                    next_state = S0;
                end
        endcase
    end
endmodule

  bit  state->next   detected
  1    S0 -> S1         0
  0    S1 -> S2         0
  1    S2 -> S1         1    <- completes "101" at positions 0-2
  1    S1 -> S1         0
  0    S1 -> S2         0
  1    S2 -> S1         1    <- completes "101" at positions 3-5
                              (overlap: bit at position 3 is reused
                              as the start of the second match)
  0    S1 -> S2         0

  Output sequence: 0,0,1,0,0,1,0